e1000.c 14 KB

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  1. /* vim: tabstop=4 shiftwidth=4 noexpandtab
  2. * This file is part of ToaruOS and is released under the terms
  3. * of the NCSA / University of Illinois License - see LICENSE.md
  4. * Copyright (C) 2017-2018 K. Lange
  5. */
  6. #include <kernel/module.h>
  7. #include <kernel/logging.h>
  8. #include <kernel/printf.h>
  9. #include <kernel/pci.h>
  10. #include <kernel/mem.h>
  11. #include <kernel/pipe.h>
  12. #include <kernel/ipv4.h>
  13. #include <kernel/mod/net.h>
  14. #include <toaru/list.h>
  15. #define E1000_LOG_LEVEL NOTICE
  16. static uint32_t e1000_device_pci = 0x00000000;
  17. static int e1000_irq = 0;
  18. static uintptr_t mem_base = 0;
  19. static int has_eeprom = 0;
  20. static uint8_t mac[6];
  21. static int rx_index = 0;
  22. static int tx_index = 0;
  23. static list_t * net_queue = NULL;
  24. static spin_lock_t net_queue_lock = { 0 };
  25. static list_t * rx_wait;
  26. static uint32_t mmio_read32(uintptr_t addr) {
  27. return *((volatile uint32_t*)(addr));
  28. }
  29. static void mmio_write32(uintptr_t addr, uint32_t val) {
  30. (*((volatile uint32_t*)(addr))) = val;
  31. }
  32. static void write_command(uint16_t addr, uint32_t val) {
  33. mmio_write32(mem_base + addr, val);
  34. }
  35. static uint32_t read_command(uint16_t addr) {
  36. return mmio_read32(mem_base + addr);
  37. }
  38. #define E1000_NUM_RX_DESC 32
  39. #define E1000_NUM_TX_DESC 8
  40. struct rx_desc {
  41. volatile uint64_t addr;
  42. volatile uint16_t length;
  43. volatile uint16_t checksum;
  44. volatile uint8_t status;
  45. volatile uint8_t errors;
  46. volatile uint16_t special;
  47. } __attribute__((packed)); /* this looks like it should pack fine as-is */
  48. struct tx_desc {
  49. volatile uint64_t addr;
  50. volatile uint16_t length;
  51. volatile uint8_t cso;
  52. volatile uint8_t cmd;
  53. volatile uint8_t status;
  54. volatile uint8_t css;
  55. volatile uint16_t special;
  56. } __attribute__((packed));
  57. static uint8_t * rx_virt[E1000_NUM_RX_DESC];
  58. static uint8_t * tx_virt[E1000_NUM_TX_DESC];
  59. static struct rx_desc * rx;
  60. static struct tx_desc * tx;
  61. static uintptr_t rx_phys;
  62. static uintptr_t tx_phys;
  63. static void enqueue_packet(void * buffer) {
  64. spin_lock(net_queue_lock);
  65. list_insert(net_queue, buffer);
  66. spin_unlock(net_queue_lock);
  67. }
  68. static struct ethernet_packet * dequeue_packet(void) {
  69. while (!net_queue->length) {
  70. sleep_on(rx_wait);
  71. }
  72. spin_lock(net_queue_lock);
  73. node_t * n = list_dequeue(net_queue);
  74. void* value = n->value;
  75. free(n);
  76. spin_unlock(net_queue_lock);
  77. return value;
  78. }
  79. static uint8_t* get_mac() {
  80. return mac;
  81. }
  82. #define E1000_REG_CTRL 0x0000
  83. #define E1000_REG_STATUS 0x0008
  84. #define E1000_REG_EEPROM 0x0014
  85. #define E1000_REG_CTRL_EXT 0x0018
  86. #define E1000_REG_RCTRL 0x0100
  87. #define E1000_REG_RXDESCLO 0x2800
  88. #define E1000_REG_RXDESCHI 0x2804
  89. #define E1000_REG_RXDESCLEN 0x2808
  90. #define E1000_REG_RXDESCHEAD 0x2810
  91. #define E1000_REG_RXDESCTAIL 0x2818
  92. #define E1000_REG_TCTRL 0x0400
  93. #define E1000_REG_TXDESCLO 0x3800
  94. #define E1000_REG_TXDESCHI 0x3804
  95. #define E1000_REG_TXDESCLEN 0x3808
  96. #define E1000_REG_TXDESCHEAD 0x3810
  97. #define E1000_REG_TXDESCTAIL 0x3818
  98. #define E1000_REG_RXADDR 0x5400
  99. #define RCTL_EN (1 << 1) /* Receiver Enable */
  100. #define RCTL_SBP (1 << 2) /* Store Bad Packets */
  101. #define RCTL_UPE (1 << 3) /* Unicast Promiscuous Enabled */
  102. #define RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */
  103. #define RCTL_LPE (1 << 5) /* Long Packet Reception Enable */
  104. #define RCTL_LBM_NONE (0 << 6) /* No Loopback */
  105. #define RCTL_LBM_PHY (3 << 6) /* PHY or external SerDesc loopback */
  106. #define RTCL_RDMTS_HALF (0 << 8) /* Free Buffer Threshold is 1/2 of RDLEN */
  107. #define RTCL_RDMTS_QUARTER (1 << 8) /* Free Buffer Threshold is 1/4 of RDLEN */
  108. #define RTCL_RDMTS_EIGHTH (2 << 8) /* Free Buffer Threshold is 1/8 of RDLEN */
  109. #define RCTL_MO_36 (0 << 12) /* Multicast Offset - bits 47:36 */
  110. #define RCTL_MO_35 (1 << 12) /* Multicast Offset - bits 46:35 */
  111. #define RCTL_MO_34 (2 << 12) /* Multicast Offset - bits 45:34 */
  112. #define RCTL_MO_32 (3 << 12) /* Multicast Offset - bits 43:32 */
  113. #define RCTL_BAM (1 << 15) /* Broadcast Accept Mode */
  114. #define RCTL_VFE (1 << 18) /* VLAN Filter Enable */
  115. #define RCTL_CFIEN (1 << 19) /* Canonical Form Indicator Enable */
  116. #define RCTL_CFI (1 << 20) /* Canonical Form Indicator Bit Value */
  117. #define RCTL_DPF (1 << 22) /* Discard Pause Frames */
  118. #define RCTL_PMCF (1 << 23) /* Pass MAC Control Frames */
  119. #define RCTL_SECRC (1 << 26) /* Strip Ethernet CRC */
  120. #define RCTL_BSIZE_256 (3 << 16)
  121. #define RCTL_BSIZE_512 (2 << 16)
  122. #define RCTL_BSIZE_1024 (1 << 16)
  123. #define RCTL_BSIZE_2048 (0 << 16)
  124. #define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
  125. #define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
  126. #define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
  127. #define TCTL_EN (1 << 1) /* Transmit Enable */
  128. #define TCTL_PSP (1 << 3) /* Pad Short Packets */
  129. #define TCTL_CT_SHIFT 4 /* Collision Threshold */
  130. #define TCTL_COLD_SHIFT 12 /* Collision Distance */
  131. #define TCTL_SWXOFF (1 << 22) /* Software XOFF Transmission */
  132. #define TCTL_RTLC (1 << 24) /* Re-transmit on Late Collision */
  133. #define CMD_EOP (1 << 0) /* End of Packet */
  134. #define CMD_IFCS (1 << 1) /* Insert FCS */
  135. #define CMD_IC (1 << 2) /* Insert Checksum */
  136. #define CMD_RS (1 << 3) /* Report Status */
  137. #define CMD_RPS (1 << 4) /* Report Packet Sent */
  138. #define CMD_VLE (1 << 6) /* VLAN Packet Enable */
  139. #define CMD_IDE (1 << 7) /* Interrupt Delay Enable */
  140. static int eeprom_detect(void) {
  141. write_command(E1000_REG_EEPROM, 1);
  142. for (int i = 0; i < 100000 && !has_eeprom; ++i) {
  143. uint32_t val = read_command(E1000_REG_EEPROM);
  144. if (val & 0x10) has_eeprom = 1;
  145. }
  146. return 0;
  147. }
  148. static uint16_t eeprom_read(uint8_t addr) {
  149. uint32_t temp = 0;
  150. write_command(E1000_REG_EEPROM, 1 | ((uint32_t)(addr) << 8));
  151. while (!((temp = read_command(E1000_REG_EEPROM)) & (1 << 4)));
  152. return (uint16_t)((temp >> 16) & 0xFFFF);
  153. }
  154. static void find_e1000(uint32_t device, uint16_t vendorid, uint16_t deviceid, void * extra) {
  155. if ((vendorid == 0x8086) && (deviceid == 0x100e || deviceid == 0x1004 || deviceid == 0x100f)) {
  156. *((uint32_t *)extra) = device;
  157. }
  158. }
  159. static void write_mac(void) {
  160. uint32_t low;
  161. uint32_t high;
  162. memcpy(&low, &mac[0], 4);
  163. memcpy(&high,&mac[4], 2);
  164. memset((uint8_t *)&high + 2, 0, 2);
  165. high |= 0x80000000;
  166. write_command(E1000_REG_RXADDR + 0, low);
  167. write_command(E1000_REG_RXADDR + 4, high);
  168. }
  169. static void read_mac(void) {
  170. if (has_eeprom) {
  171. uint32_t t;
  172. t = eeprom_read(0);
  173. mac[0] = t & 0xFF;
  174. mac[1] = t >> 8;
  175. t = eeprom_read(1);
  176. mac[2] = t & 0xFF;
  177. mac[3] = t >> 8;
  178. t = eeprom_read(2);
  179. mac[4] = t & 0xFF;
  180. mac[5] = t >> 8;
  181. } else {
  182. uint8_t * mac_addr = (uint8_t *)(mem_base + E1000_REG_RXADDR);
  183. for (int i = 0; i < 6; ++i) {
  184. mac[i] = mac_addr[i];
  185. }
  186. }
  187. }
  188. static int irq_handler(struct regs *r) {
  189. uint32_t status = read_command(0xc0);
  190. if (!status) {
  191. return 0;
  192. }
  193. irq_ack(e1000_irq);
  194. if (status & 0x04) {
  195. /* Start link */
  196. debug_print(E1000_LOG_LEVEL, "start link");
  197. } else if (status & 0x10) {
  198. /* ?? */
  199. } else if (status & ((1 << 6) | (1 << 7))) {
  200. /* receive packet */
  201. do {
  202. rx_index = read_command(E1000_REG_RXDESCTAIL);
  203. if (rx_index == (int)read_command(E1000_REG_RXDESCHEAD)) return 1;
  204. rx_index = (rx_index + 1) % E1000_NUM_RX_DESC;
  205. if (rx[rx_index].status & 0x01) {
  206. uint8_t * pbuf = (uint8_t *)rx_virt[rx_index];
  207. uint16_t plen = rx[rx_index].length;
  208. void * packet = malloc(plen);
  209. memcpy(packet, pbuf, plen);
  210. rx[rx_index].status = 0;
  211. enqueue_packet(packet);
  212. write_command(E1000_REG_RXDESCTAIL, rx_index);
  213. } else {
  214. break;
  215. }
  216. } while (1);
  217. wakeup_queue(rx_wait);
  218. }
  219. return 1;
  220. }
  221. static void send_packet(uint8_t* payload, size_t payload_size) {
  222. tx_index = read_command(E1000_REG_TXDESCTAIL);
  223. debug_print(E1000_LOG_LEVEL,"sending packet 0x%x, %d desc[%d]", payload, payload_size, tx_index);
  224. memcpy(tx_virt[tx_index], payload, payload_size);
  225. tx[tx_index].length = payload_size;
  226. tx[tx_index].cmd = CMD_EOP | CMD_IFCS | CMD_RS; //| CMD_RPS;
  227. tx[tx_index].status = 0;
  228. tx_index = (tx_index + 1) % E1000_NUM_TX_DESC;
  229. write_command(E1000_REG_TXDESCTAIL, tx_index);
  230. }
  231. static void init_rx(void) {
  232. write_command(E1000_REG_RXDESCLO, rx_phys);
  233. write_command(E1000_REG_RXDESCHI, 0);
  234. write_command(E1000_REG_RXDESCLEN, E1000_NUM_RX_DESC * sizeof(struct rx_desc));
  235. write_command(E1000_REG_RXDESCHEAD, 0);
  236. write_command(E1000_REG_RXDESCTAIL, E1000_NUM_RX_DESC - 1);
  237. rx_index = 0;
  238. write_command(E1000_REG_RCTRL,
  239. RCTL_EN |
  240. (read_command(E1000_REG_RCTRL) & (~((1 << 17) | (1 << 16)))));
  241. }
  242. static void init_tx(void) {
  243. write_command(E1000_REG_TXDESCLO, tx_phys);
  244. write_command(E1000_REG_TXDESCHI, 0);
  245. write_command(E1000_REG_TXDESCLEN, E1000_NUM_TX_DESC * sizeof(struct tx_desc));
  246. write_command(E1000_REG_TXDESCHEAD, 0);
  247. write_command(E1000_REG_TXDESCTAIL, 0);
  248. tx_index = 0;
  249. write_command(E1000_REG_TCTRL,
  250. TCTL_EN |
  251. TCTL_PSP |
  252. read_command(E1000_REG_TCTRL));
  253. }
  254. static void e1000_init(void * data, char * name) {
  255. debug_print(E1000_LOG_LEVEL, "enabling bus mastering");
  256. uint16_t command_reg = pci_read_field(e1000_device_pci, PCI_COMMAND, 2);
  257. command_reg |= (1 << 2);
  258. command_reg |= (1 << 0);
  259. pci_write_field(e1000_device_pci, PCI_COMMAND, 2, command_reg);
  260. debug_print(E1000_LOG_LEVEL, "mem base: 0x%x", mem_base);
  261. eeprom_detect();
  262. debug_print(E1000_LOG_LEVEL, "has_eeprom = %d", has_eeprom);
  263. read_mac();
  264. write_mac();
  265. debug_print(E1000_LOG_LEVEL, "device mac %2x:%2x:%2x:%2x:%2x:%2x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  266. unsigned long s, ss;
  267. uint32_t ctrl = read_command(E1000_REG_CTRL);
  268. /* reset phy */
  269. write_command(E1000_REG_CTRL, ctrl | (0x80000000));
  270. read_command(E1000_REG_STATUS);
  271. relative_time(0, 10, &s, &ss);
  272. sleep_until((process_t *)current_process, s, ss);
  273. switch_task(0);
  274. /* reset mac */
  275. write_command(E1000_REG_CTRL, ctrl | (0x04000000));
  276. read_command(E1000_REG_STATUS);
  277. relative_time(0, 10, &s, &ss);
  278. sleep_until((process_t *)current_process, s, ss);
  279. switch_task(0);
  280. /* Reload EEPROM */
  281. write_command(E1000_REG_CTRL, ctrl | (0x00002000));
  282. read_command(E1000_REG_STATUS);
  283. relative_time(0, 20, &s, &ss);
  284. sleep_until((process_t *)current_process, s, ss);
  285. switch_task(0);
  286. /* initialize */
  287. write_command(E1000_REG_CTRL, ctrl | (1 << 26));
  288. /* wait */
  289. relative_time(0, 10, &s, &ss);
  290. sleep_until((process_t *)current_process, s, ss);
  291. switch_task(0);
  292. debug_print(E1000_LOG_LEVEL, "back from sleep");
  293. uint32_t status = read_command(E1000_REG_CTRL);
  294. status |= (1 << 5); /* set auto speed detection */
  295. status |= (1 << 6); /* set link up */
  296. status &= ~(1 << 3); /* unset link reset */
  297. status &= ~(1UL << 31UL); /* unset phy reset */
  298. status &= ~(1 << 7); /* unset invert loss-of-signal */
  299. write_command(E1000_REG_CTRL, status);
  300. /* Disables flow control */
  301. write_command(0x0028, 0);
  302. write_command(0x002c, 0);
  303. write_command(0x0030, 0);
  304. write_command(0x0170, 0);
  305. /* Unset flow control */
  306. status = read_command(E1000_REG_CTRL);
  307. status &= ~(1 << 30);
  308. write_command(E1000_REG_CTRL, status);
  309. relative_time(0, 10, &s, &ss);
  310. sleep_until((process_t *)current_process, s, ss);
  311. switch_task(0);
  312. net_queue = list_create();
  313. rx_wait = list_create();
  314. e1000_irq = pci_get_interrupt(e1000_device_pci);
  315. irq_install_handler(e1000_irq, irq_handler, "e1000");
  316. debug_print(E1000_LOG_LEVEL, "Binding interrupt %d", e1000_irq);
  317. for (int i = 0; i < 128; ++i) {
  318. write_command(0x5200 + i * 4, 0);
  319. }
  320. for (int i = 0; i < 64; ++i) {
  321. write_command(0x4000 + i * 4, 0);
  322. }
  323. #if 0
  324. /* This would rewrite the MAC address... */
  325. write_command(0x5400, *(uint32_t*)(&mac[0]));
  326. write_command(0x5404, *(uint16_t*)(&mac[4]));
  327. write_command(0x5404, read_command(0x5404) | (1 << 31));
  328. #endif
  329. write_command(E1000_REG_RCTRL, (1 << 4));
  330. init_rx();
  331. init_tx();
  332. /* Twiddle interrupts */
  333. write_command(0x00D0, 0xFF);
  334. write_command(0x00D8, 0xFF);
  335. write_command(0x00D0,(1 << 2) | (1 << 6) | (1 << 7) | (1 << 1) | (1 << 0));
  336. relative_time(0, 10, &s, &ss);
  337. sleep_until((process_t *)current_process, s, ss);
  338. switch_task(0);
  339. int link_is_up = (read_command(E1000_REG_STATUS) & (1 << 1));
  340. debug_print(E1000_LOG_LEVEL,"e1000 done. has_eeprom = %d, link is up = %d, irq=%d", has_eeprom, link_is_up, e1000_irq);
  341. init_netif_funcs(get_mac, dequeue_packet, send_packet, "Intel E1000");
  342. }
  343. static int init(void) {
  344. pci_scan(&find_e1000, -1, &e1000_device_pci);
  345. if (!e1000_device_pci) {
  346. debug_print(E1000_LOG_LEVEL, "No e1000 device found.");
  347. return 1;
  348. }
  349. /* This seems to always be memory mapped on important devices. */
  350. mem_base = pci_read_field(e1000_device_pci, PCI_BAR0, 4) & 0xFFFFFFF0;
  351. for (size_t x = 0; x < 0x10000; x += 0x1000) {
  352. uintptr_t addr = (mem_base & 0xFFFFF000) + x;
  353. dma_frame(get_page(addr, 1, kernel_directory), 1, 1, addr);
  354. }
  355. rx = (void*)kvmalloc_p(sizeof(struct rx_desc) * E1000_NUM_RX_DESC + 16, &rx_phys);
  356. for (int i = 0; i < E1000_NUM_RX_DESC; ++i) {
  357. rx_virt[i] = (void*)kvmalloc_p(8192 + 16, (uint32_t *)&rx[i].addr);
  358. debug_print(E1000_LOG_LEVEL, "rx[%d] 0x%x → 0x%x", i, rx_virt[i], (uint32_t)rx[i].addr);
  359. rx[i].status = 0;
  360. }
  361. tx = (void*)kvmalloc_p(sizeof(struct tx_desc) * E1000_NUM_TX_DESC + 16, &tx_phys);
  362. for (int i = 0; i < E1000_NUM_TX_DESC; ++i) {
  363. tx_virt[i] = (void*)kvmalloc_p(8192+16, (uint32_t *)&tx[i].addr);
  364. debug_print(E1000_LOG_LEVEL, "tx[%d] 0x%x → 0x%x", i, tx_virt[i], (uint32_t)tx[i].addr);
  365. tx[i].status = 0;
  366. tx[i].cmd = (1 << 0);
  367. }
  368. create_kernel_tasklet(e1000_init, "[e1000]", NULL);
  369. return 0;
  370. }
  371. static int fini(void) {
  372. return 0;
  373. }
  374. MODULE_DEF(e1000, init, fini);
  375. MODULE_DEPENDS(net);